StateMachine Modeling For HDLs

To efficiently generate Hardware Description Language (HDL) code from StateMachine models, apply the design practices described in this topic. Hardware Description Languages include VHDL, Verilog and SystemC.

In an HDL StateMachine model, you might expect to:

Designate Driving Triggers
Establish Port–Trigger Mapping
Add to Active State Logic

Operations

Operation	Description	See also
Designate Driving Triggers	A 'Change' Trigger is deemed to be an asynchronousTrigger if: - There is a transition from the actual SubMachine State (which encapsulates the actual logic) that it triggers, and - The target State of that transition has a self transition triggered by the same Trigger Asynchronous Triggers should be modeled according to this pattern: - The Trigger should be of type Change (specification: True / False) - The active State (SubMachine State) should have a transition triggered by it - The target State of the triggered transition should have a self transition with the same Trigger A Trigger of type 'Time', which triggers the transitions to the active state (SubMachine State), is deemed to be the Clock; the specification of this trigger should conform to the target language: - VHDL - rising_edge / falling_edge - Verilog - posedge / negedge - SystemC - positive / negative	State Machine Diagrams Trigger
Establish Port-Trigger Mapping	After successfully modeling the different operating modes of the component, and the Triggers associated with them, you must associate the Triggers with the component's Ports. A Dependency relationship from the Port to the associated Trigger is used to signify that association.
Active State Logic	Designating the driving Trigger and establishing the Port-Trigger mapping put in place the preliminaries required for efficiently interpreting the hardware components. The actual StateMachine logic is now modeled within the Active (SubMachine) state.

Operation

Description

See also

Designate Driving Triggers

A 'Change' Trigger is deemed to be an asynchronousTrigger if:
     - There is a transition from the actual SubMachine State (which
        encapsulates the actual logic) that it triggers, and
     - The target State of that transition has a self transition triggered
         by the same Trigger

Asynchronous Triggers should be modeled according to this pattern:
     - The Trigger should be of type Change (specification: True / False)
     - The active State (SubMachine State) should have a transition
         triggered by it
     - The target State of the triggered transition should have a self
         transition with the same Trigger

A Trigger of type 'Time', which triggers the transitions to the active state (SubMachine State), is deemed to be the Clock; the specification of this trigger should conform to the target language:
     - VHDL - rising_edge / falling_edge
     - Verilog - posedge / negedge
     - SystemC - positive / negative

State Machine Diagrams Trigger

Establish Port-Trigger Mapping

After successfully modeling the different operating modes of the component, and the Triggers associated with them, you must associate the Triggers with the component's Ports.

A Dependency relationship from the Port to the associated Trigger is used to signify that association.

Active State Logic

Designating the driving Trigger and establishing the Port-Trigger mapping put in place the preliminaries required for efficiently interpreting the hardware components.

The actual StateMachine logic is now modeled within the Active (SubMachine) state.

Notes

To be able to generate code from behavioral models, all behavioral constructs should be contained within a Class
The current code generation engine supports only one clock Trigger for a component

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